As a programmer, I always wanted a cpu which instead of having n 64 bit registers, had a single register with 2^m bits, which could be split in arbitrary length sub registers, not all the same size, and could be treated as an array of bits, or a swar machine

This is a "build it and they will come" project. It's not a "we put the inner loop of ML entirely in hardware" project. That would make more sense technically. You could cram a lot of little independent neural net inference units on one chip. But if it was pitched that way, the questions would be "Why isn't NVidia doing this", and "After you do it, what keeps NVidia from doing it". There are lots of people pitching "AI chips", with modest success.

The history of general-purpose massively parallel machines isn't good. From the Illiac IV to the Playstation 3, there's been dud after dud in this space. You can build them, but the users don't come. This sort of architecture is great if you have some specific problem that parallelizes, such as finite-element analysis or neural networks.

(I've used an NCube, and I kind of liked the Transputer concept. But both were dead ends.)

I thought greenarrays was incredibly cool. (144 native-forth cores on a chip)

I loved the mill architecture (self declared clean sheet cpu).

I thought transmeta had a good chance because they could inline across kernel boundaries.

But none of them was special enough.

This feels a decade late. I don't really see the value prop for customers in 2026 (or realistically, 2030+). Let's say I'm willing to rewrite all my software to a language that compiles down into interaction nets. Why don't I use HVM2 instead and buy GPUs from Nvidia? If I just want to use an exotic architecture, AMD is shipping dataflow processors at scale today, and they'll license related IP. And if I just want a massively parallel architecture to run my existing ML code on, I could just rent google cloud TPUs instead.

Who's the customer that wants an exotic architecture on an old process node running a custom programming language half a decade from now?

Hmm. The story over at https://millcomputing.com/ always looked compelling.

Pitchbook shows it as "Out of Business" since 2019.

This is my first time hearing about Vine - https://vine.dev/ I have to say the landing page is terrible, at least show an example of the language.

I always wonder where will x86 be in 10 or 20 years time. As data paths widen for SIMD, how many can they possibly cram , such as more generations of wider and wider groups of instruction with different opcodes and characteristics.

From the URL:

"Instead of starting from a sequential design, we’re building our processor to have thousands of cores operating in parallel. This requires moving beyond the notion of shared mutable memory and linear instruction sequences. To make this possible, we’re working in tandem on the open-source language Vine, which has been designed from the beginning to target a new wave of parallel-first architectures."

I wish them well but from their Vine language docs:

"For example, a < b < c is equivalent to (a < b) & (b < c)"

So how do you parallelize that? You can run the first part on 2 cores in parallel, but there is still a single check, a single cache, a single CPU for this to go through to complete the operation, right?

Am I missing something?

I couldn't find any parallel constructs in the language. So, as I understand it, it's a regular language that gets compiled into a graph, and the runtime parallelizes the execution of that graph.

This factorial won't run any faster with more cores, since each step depends on the previous one:

  fn fat(n: N64) -> N64 {
    if n <= 1 {
      1
    } else {
      n * fat(n - 1)
    }
  }

This other version can run in parallel, but only because the algorithm was deliberately written that way:

  fn fat(n: N32) -> Nat {
    if n == 0 { 1 as Nat } else { prod(1, n) }
  }

  fn prod(lo: N32, hi: N32) -> Nat {
    if lo == hi {
      lo as Nat
    } else {
      let m = (lo + hi) / 2;
      let left = prod(lo, m);
      let right = prod(m + 1, hi);
      left * right
    }
  }

So the programmer still has to think about parallelism; the language just removes the need for threads and locks.

Also, as the graph grows, sequential dependencies still limit the speedup, and more cores means more data moving between them. How does the hardware deal with that?

Wasn't that what RISCV was supposed to do? apologies, dumb question

Isn't this basically a GPU?

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How will this be better than RISC V?

I'm quite interested to see how this evolves. But part of me is still being sad, because hardware is rarely the bottleneck these days - as opposed to software.

Have you seen the new CPU architecture? It's on Mill. It's literally on Transputer. It's on Rock with Sun. It's literally on AMULET. You can probably find it on Itanium. Dude it's on Tesla. It's a CDC STAR original. It's on E1. You can program it on E1. You can go to E1 and program it. Get onto E1 right now. Go to E1. Dive into E1. You can E1 it. It's on E1. E1 has it for you. E1 has it for you.

In all seriousness congratulations on finding $30 million to launder and lose immediately. Hope your Porsche runs good.

Let's not call it a CPU if it doesn't have SoTa single threaded performancr

> Sources say that the company is already discussing a fast follow-up raise that would potentially value the firm at more than $1 billion. Neither round has previously been reported. Benchmark declined to comment.

https://www.newcomer.co/p/scoop-benchmark-backs-early-stage

VC is such a meme lmao. What’s next, Sam gonna acquire the company? No product needed!

it’s the Transputer again, or the Emotion Engine again, depending on how old you are

FTA:

"Instead of starting from a sequential design, we’re building our processor to have thousands of cores operating in parallel. This requires moving beyond the notion of shared mutable memory and linear instruction sequences. To make this possible, we’re working in tandem on the open-source language Vine, which has been designed from the beginning to target a new wave of parallel-first architectures."

Reminds me of the Transputer and Occam. Each transputer had 4 comm links to form a flexible network of processors and Occam supported parallelism. Also one of the first languages to use indentation for block structures.

For a long time I missed their folding editor.

Maybe now the cpu arena is a patent graveyard instead of a patent minefield, some fresh developments can appear.

let's re-do the OS too. we only need about 10 syscalls. authorization is totally backwards (look how android runs a user per process).

Was about time we had another Transmeta.

Bet you they will turn into yet another ML accelerator company within the year.

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TL;DR: it's basically Niagara/GreenArrays/etc again.

Not sure why this one will succeed where its forebears didn't.