GPT-Synopsys brings together OpenAI frontier models with Synopsys' EDA technology and domain expertise, enabling the specialized model [to] directly operate Synopsys' tools. Engineers will delegate design objectives … with agents running tools, interpreting results, implementing changes, and iterating toward verified outcomes for engineer review.
I do agree that a lot of engineers who want to do everything the old manual way are about to get really frustrated.
I don't think this is as universal as you say. There are a lot of engineers who are excited and happy to use these tools. Leave the bubbles of Hacker News, Lobsters, and similar sites and a lot of people are embracing these tools.
You also skipped the step where someone needs to direct the design. In the pre-LLM era it was commonly accepted that engineers who advanced to very senior roles would become less connected to the implementation details and more connected to steering, reviewing, and directing. Only a few years ago Hacker News was full of anecdotes about staff engineers who barely wrote code any more. Those people will have no problem switching to a new world where LLMs are handling implementation details.
Why people are so eager to surrender their birthright to the machines for the mess of pottage?
GPT-Company name brings together frontier AI models with Company's XYZ technology and domain expertise, enabling the specialized model [to] directly operate Company's tools. Engineers will delegate design objectives … with agents running tools, interpreting results, implementing changes, and iterating toward verified outcomes for engineer review.
While I think SWEs(yeah, not HW/chip but that's not my field) are cooked in 5 years, I think we'll be quite busy in the meantime fixing all the bugs that AI finds.
Maybe that's the job of software engineering moving forward.
Client: Hey, we have got these 125 microservices created by our agents and for the last 25 days they got stuck and can't add any new feature without breaking things, can you take this?
Eng: Sure, lets sign a 24 month contract, my rate is 250$/hr
Client: Sounds good
I've been using Astra and Opus 5.5 all week and I still have to intervene and tell them to do something different all the time.
I think the people whose SWE jobs consisted of simple features, bug fixes, or tweaking .toml until the server works are on their way out.
Someone needs to steer the LLMs around for now, though. There is a very long tail of non-trivial work and expertise that can't yet be replaced by a CEO telling the LLM to make the product work. There are many CEOs trying to do that right now and, outside of very simple CRUD apps, it doesn't work yet.
The challenge as I see it is in shifting checks further left, but actual mitigation is just not really an issue any more.
If costs go down enough,because of LLM's and possible manufacturing innovations, more chips will be designed, so maybe this will partially offset job loses.
So let's see.
This is HN mentality. But it is not how it always works. The first thought isn't we can make more money tomorrow by building more faster. It is we can make more money today by laying off all the people that we don't need now. Short-termism is the rule.
I wish this was hubris, but no. I would genuninely be happy to not have to do other people's work for them on top of mine.
So we now have AI powered chip design tools that make chip design cheaper, but because of AI, chip manufacturing has become so expensive, that we can't afford it anymore.
Nice.
Manufacturers choosing not to scale with demand or not being able to scale with demand
Is what constrained the supply.
Hopefully will be fixed within a decade , then it’s cool new stuff all the way.
In a vacuum, that would make sense.
But looking at how the industry works, the number of defunct companies, and how the whole industry got concentrated on the conservative companies, you start to understand that the reason they still exist is mainly because they don't ride fad waves.
It's not like chip manufacturing is a spot instance on AWS that you spin up and down when needed; these are multi-year, multi-billion dollar investments that require long-term demand studies. The AI approach of requesting a whole fab of demand for the next 5 years with a letter from Jason Hwang that says "trust it, bro" does not bring as much confidence as it appears.
If AI made it 100x faster and cheaper to build software, you suddenly have an explosion of software that need to be hosted. So companies like AWS/iOS App Store/cloud companies benefit.
If AI makes designing chips 100x faster and cheaper, you will have an explosion of custom chips for all sorts of applications. These chips still need to be physically made at TSMC, Intel, or Samsung.
Apple says it takes 3-4 years to design each Apple Silicon generation.[0] So the M6 was being designed in 2022-2023 already. Reports are that it costs hundreds of millions to a billion to design a cutting edge chip from scratch to finish.[0]
The cool thing is that we'll have niche ASIC chips for accelerating special applications that previously didn't have big of a market for someone to make a profit on. This is the same thing with software today. It's much easier to build custom software for a small niche and be profitable today than in 2022.
Maybe some day, a kid in his garage can just tell an AI to design a custom chip, send it to TSMC, and get the chip in the mail in a few weeks.
And given that Moore's Law is essentially dead in terms of density scaling, having an AI to automatically optimize the hell out of design and squeeze as much performance as possible out of the transistors could help us have a few more years of nice performance increase.
[0]https://fireflies.ai/blog/johny-srouji-and-john-ternus-inter...
[1]https://www.granitefirm.com/blog/us/2023/04/29/cost-of-chip-...
This isn't software. The time, labor, and equipment costs of the first wafer dwarf the redesign cost, so it makes sense to get it right the first time. What if every build, compile, and link cost you $10M and 1 month? How would that change your work flow?
Most of the "AI" design tools today are focused on verification, validation and layout, which makes a lot of sense. They might help with architecture in the future (or making something high yield AND easy to fix in metal)?
You could run a small design on an MPW shuttle to reduce these costs, but your TTM get's longer, the yields won't be as high, and if you go to mass production you still face the huge mask costs.
Another place this might make some sense is reworking old large die 130nm designs on 8" wafers to be newer 28mm designs on 12", there are a LOT of those. The mask costs are lower, the design is well understood with lots of process margin, and wafer/yield costs could be modeled and favorable. Of course analog scaling is a whole separate kettle of fish.
If people have millions of new chip designs that need making, perhaps that will be motivation to invent a new way of making chips. It might not be better at manufacturing a billion of the same chip, but maybe it’s better at producing a billion different chips. Then every HFT could have their own chip and people could try out all kinds of new designs without committing a fortune.
There's a reason e-beam lithography is only used to make masks, and why it's one of the most expensive parts of the manufacture.
The problem isn't lithography, though, it's all of the adjacent processes (ion implantation and a dozen other things) that are fab/process-specific and require even more complicated/expensive equipment.
Shuttle runs give you a true-to-process tapeout and are dirt cheap, so only universities and the like bother with direct-write.
That's for the most advance tech (sub 10nm and such). There is a lot of fab for chips that do not require the latest and greatest. If LLMs make it easier / more accessible to design ASIC, I think those fabs will be the one who will benefit the most.
Also : create proprietary locked down eda->no data to train models->models suck at it->reach out to ai lab to rl on it -> expect users to pay for eda and the model.
EXACTLY, prepare to self deport immediately, push <proceed> to execute
I am not sure if Nvidia want to send their chip designs to OpenAI.
Toolcalls will end up disappearing to the other side and then you can download the end result - at a price - or arrange for manufacturing, but you'll have no idea about what is in the nice & shiny black box.
Like for a Arm microcontroller design, do engineers thoroughly test and formally prove the correct functionality of every component? If that's the case, why silicon errata is a thing?
Why there are still errata for silicon
1. Writing a formal specification of your intended behavior is hard and the best verification tool doesn't help when your assertions don't encode the required or intended behavior. So even with 100% formal coverage, you would still get erratas. And some people don't write any formal verification, instead working with a simulation based approach (either hand-written test cases or random stimulus simulation) 2. Computation complexity of formal verification is exponential. At some point you simply can't formally prove the behavior of a design, because it just won't run on your server. 3. There's different levels of formal verification, not all of them are in the spec -> behavior path. For example, you could classify automated checks like logic equivalence between the synthesis netlist and RTL code as a formal verification. But that checks if the optimizer in the synthesis tool was correct, not that you wrote the correct RTL.
The most common type that is used would probably be logical equivalence checking. Proving RTL and a netlist are equivalent is useful for catching synthesis bugs.
Or proving two netlists are equivalent after inserting test functions directly into a netlist, or some other netlist edit.
Property checking is what I use the most. You can check these during simulation which I wouldn’t call “formal” but you can also prove them using tools that use SAT solvers and whatnot to prove things mathematically.
As always, the tricky part of verification is writing the correct test or model. With formal we can use SystemVerilog assertions to write properties and sequences, but the difficulty in getting them right goes from trivial -> inscrutable very quickly.
It’s extreme easy to write assertions that pass and never realize your assertion was not doing what you thought and you weren’t proving what you meant to.
I haven’t used some of the more advanced tools so maybe they have ways to make this easier. But because of this I tend to just write assertions that are pretty easy to understand at a glance, and therefore closer to the trivial side of things.
If a peer has to solve a sudoku puzzle in their head to understand your work, then it’s unlikely the peer review will be worth anything. So I do what I can to make my work understandable at a glance (from a competent peer in the industry).
Of course making something simple can be quite challenging and often takes more time than leaving something complex and opaque.
I’ve never been involved in the foundry side of the work, and for ASICs, that is often half of the schedule.
Why the overall market cap is smaller than both Synopsys and Ansys combined before the merger still beats me tho.
DRC/LVS/PEX/SPICE are deterministic, but the tools themselves are not without faults.
If you have a flaw in the RTL and need to do a respin it can add 3+ months to the lead time of a new product. Allowing GPT to iterate through this kind of cycle seems economically infeasible unless you have an enormous amount of spare EUV capacity (you don't).
Can't wait for vibe coded SoCs.
You can already make (tiny) chips for a somewhat affordable cost with tiny tapeout. But that's still not nearly as cheap as PCB prototypes and with much longer wait times.