That being said, I am not sure what’s the killer application for this technology, and without such application adoption is unlikely.
Imagine (this is a fantasy pitch but potentially achievable for some use cases) wanting to run a larger llm and all you have to do is buy more RAM so it fits.
AI: "Sorry, all the hardware is made for running AI."
Isn't this how it works today already? Granted you wanted to run it on RAM rather than VRAM.
According to article/Samsung RAM dies inside can provide way more bandwidth, they're limited by external interface / bus width:
> Together, they can utilize the chip’s internal bandwidth across all 16 banks, which comes out to 614 GB/s. For comparison, regular DRAM accesses can hit two banks in parallel and max out at 76.8 GB/s.
And that's just for single 64-bit IC. So way faster and more power efficient.
Build it, and they will come ;)
Add a new set of CPU instructions like “rep macb”
...and it's been long enough now, that I can say there was an effort to implement this on standard x86 memory controllers and have the existing string instructions do so, back in the days of SDR SDRAM, but the tradeoffs weren't (yet) in favour.