68 pointsby jacktang8 hours ago5 comments
  • lefra2 hours ago
    The graphs are beautiful, however they're independent of the language (because they're a visualization of the resulting gates). You could get the same graphs from VHDL or Verilog.

    I don't like the "fallback" mechanism, because it will be used when "something goes wrong", without being specific about exactly under what conditions should the fallback happen. Maybe I made a mistake, "something" fails at a step I didn't expect, and this will silently implement in a way I didn't mean (maybe the result is even correct, just using way more gates than needed).

  • freakynit4 hours ago
    I made this comment a few days back: https://news.ycombinator.com/item?id=48668760

    Is this kinda similar in nature?

  • hosel7 hours ago
    The visualizations are stunning!
  • bbminner5 hours ago
    Honestly this is the first time I am seeing this kind of work that i genuinely like. Most fractal and other kinds of self repeating results are not that interesting at all to me.
  • amoshebb4 hours ago
    Not really an HDL, as currently it has no concept of actually connecting the nodes. Each edge is an arbitrary number of conductors with no constraints on routing or timing. Curious to see where this goes though
    • jy148982 hours ago
      > Although logic connectivity is not layout-dependent in the current prototype, we envision a future where physical proximity directly influences or determines logical connections. In this ultimate view, the circuit behaves like a digital organism whose physical form and logical connections evolve together under local structural constraints.
      • lefra2 hours ago
        Once any HDL is translated to a bunch of primitives (gates, LUTs, flip-flops, etc), that's the job of an automated place-and-route, which already exist. It's independent of the starting language.
    • light_hue_13 hours ago
      This is the view of an HLD that someone without any actual HLD experience would have.