Article reeks of LLM mannerisms in a pretty obnoxious way. I read it anyways and surprise surprise, it boils down to:

- Ridiculously NP problem space that we guess and check with ML heuristics.

- Problem: not enough training data

Cool enough work, but the LLM generated fluff in the article really takes away from it.

I think I saw a few years ago another version of this for IC and simpler CPUs.

For me the takeaway is:

- the libraries we use for chip design are small and reproducible, and we can reason about and account for their properties properly, so a designer can minimize design time by reusing small bits that are well understood and ship better architectures faster

- the optimal structures that would allow a design to minimize power use/maximize efficiency and at the same time guarantee highest performance are basically spread-out structures that humans could hardly conceive and reason about, because they look more like roots in a natural ecosystem rather than nice blocks of cut stone that you can stack (not to mention that developing a way to fabricate these chips can be harder)

Template libraries pushed chip design this far, and perhaps there some more to come, but we're hitting a wall where structures are becoming small enough that using libraries is starting to hinder the ability to scale further. These spread-out structures minimize interference and hot-spot creation by separating components that are normally "on" together, allowing better thermal distribution (and thus budget) and reducing interference by physical distance or "off" components, thus unlocking higher clocks and better efficiency.

And people will continue to try to make the misguided point that AI is and will always be unable to do anything novel, especially from an arts perspective. Funny.