Extracting a UART Password via SPI Flash Instruction Tracing(zuernerd.github.io)

55 pointsby Eduard7 hours ago6 comments

userbinator44 minutes ago
We could try to find this loading using static analysis, but remember that I’m not comfortable reverse engineering this firmware, and I want to demonstrate a more dynamic approach.
Perhaps this is a "two types of people" situation, but I would absolutely not do that; once you dump the flash you can analyse and inspect it carefully at your leisure as it is otherwise inert, but messing around with the device itself presents a very real risk of accidentally bricking it.
Aurornis3 hours ago
It’s too bad Saleae prices are so high now. Their original models launched at a very affordable price point but that’s long gone.
In the past they’ve offered discounts to students and contractors if you know where to look and how to ask: https://blog.saleae.com/saleae-discounts/ If anyone is considering one, it’s worth a try to see if they still honor this.
The alternative logic analyzers mentioned in this article look interesting, but the software side leaves a lot to be desired. Some people get along okay with PulseView (or forks, like in this article) but I never enjoy using it.
ggman hour ago
I know a community who invested in an Arm sbc to do photo management with a locked bootloader running a locked Linux kernel where the developers have walked away (Ukraine war)
Its the "Monument" device. The users would love it if somebody unlocked things this way.
qingcharles2 hours ago
Interesting that someone else had previously found it too -- I wonder how they got hold of it?
https://github.com/up-n-atom/SWTG118AS/commit/514483b9c9e4d6...
direwolf205 hours ago
Very nice!
An 8051 with XIP SPI flash - that must be ancient tech.
- lloydatkinson3 hours ago
  Not necessarily, there are 8051 soft cores you can get for your FPGA/ASIC.
dsrtslnd235 hours ago
do you know the SPI clock frequency? I am trying to figure out the sampling rate required to reliably capture the trace. That determines the tier of logic analyzer needed I guess.
- Neywiny5 hours ago
  A few ways:
  1. Read the datasheets. Some parts only support certain frequencies, so find the minimum of the master and slave frequencies. 2. Check at boot. Most devices boot slowly for the first few transactions then speed up. So if you saw valid data then aliasing, get a better kit. 3. Start high. I think the fastest serial memory devices cap out at 250 MHz DDR for volatile and 200 for non-volatile. So even a digital discovery (which I think is the best LA for high speed bursts) can deal with it
- mschuster9131 minutes ago
  In a pinch, a frequency counter should be able to give you at least a ballpark estimate.
- Gracana4 hours ago
  article says 60MHz
- rasz4 hours ago
  in this particular case "We need to be able to capture 60 MHz SPI."
  For something cheap and capable you could try building rp2350 based https://github.com/gusmanb/logicanalyzer, goes up to 400Ms/s. Its just a Pico1/2 with a level shifter board
  "This is an affordable logic analyzer capable of reaching up to 400Mhz of sampling speed. The analyzer uses a Pico/Pico2 as its core. The analyzer offers 24 channels but can be chained up to 5 devices allowing the sampling of up to 120 channels at once."
  I havent played with their software yet, but I have a ton of experience with pulseview and while its feature rich it is sluggish and not suited for high speed big volume acquisitions (especially the dreadfully Python 3.4 plugins and Im saying this as an author of one of the plugins) so anything written even half competently might be better.