Not the gdb support via jtag that software engineers need, they have that. But the various manufacturing test suites, which do modify gate netlists, and automated circuit characterization techniques that electrical engineers and the manufacturing engineers use.

But I was actually pleasantly surprised by how close they are.

If you can get a "library" from somewhere (like the one Google released from Skywater), then you can use static timing analysis on the interconnect between the library blocks. Performance metrics will all be mediocre, but it will be relatively quick to design and cheap to produce if you have sufficient volumes. This is why so many of the RISC-V processor implementations suck.

If you want to design analog, RF, or high-speed, then the expensive tooling is required. You need especially need DRC and extraction (parasitics from passives, transistor numbers, etc.) for proper analysis and design.