A little over 16 hours? That's suspiciously short. The endurance vs retention curve isn't clear from this article either; they say "10 years" and "5.5 million cycles" but it seems more like you either get 10 years and 1 cycle, or 5.5M cycles to immediate failure with no regard to retention.
It reminds me of this old paper on testing USB drives for endurance, where they just hammered at the flash until it failed to program immediately and "concluded" that the endurance was many orders of magnitude higher than the manufacturer's specifications, with no attention paid to retention at all: https://www.usenix.org/event/fast10/tech/full_papers/boboila...
Surely if they already have a test setup, then having a test last for 600,000 seconds isn't very hard?
Things that look linear for a short period end up being exponential over longer periods. I don't think we can assume linear extrapolation here. There could be physics at play where exponential degeneration of the voltage occurs.
Its a good start of a test. But it seems weird in that a paper like this would have taken much more than ~1 week to write, so making a test last ~1 week for their calculations seems within the feasibility of this group. But its oddly missing data.
Adding a couple of percent of ECC data tends to 10x retention anyway, so there is a direct engineering trade off between retention and capacity.
Researchers develop picosecond-level flash memory device (19.04.2025)
Why are we constrained to such a relatively small amount of L1 cache? What would stop us from extending this arbitrarily?
There are power, speed, and complexity trade-offs in cache design. Here were a few of them:
Direct-mapping is the simplest approach, and means a given address can only exist in one location, but a problem occurs when two addresses map to the same cache line - one is evicted even if there's plenty of space in the cache elsewhere.
What if we built an associative cache, where every line had an address indicator? Then we can fully use the cache space. But it's far more complicated to search: a miss requires checking every cacheline. If it's fast, so does a hit.
Many systems today use a mix. Smaller caches are often direct mapped. Larger caches tend to use a combination of 2-8 direct-mapped caches where an address can be searched in at the same time, or within a few cycles of each other.
Another problem is evictions becoming a future cache miss. With only a large L1, a cacheline was either in fast L1 or in DRAM. There's often a write buffer or victim cache between them to try to hide dirty eviction latency, but a subsequent fetch will pay the DRAM access cost. As we scale the cache size up, L1 access speed becomes challenging and eventually it's more effective to limit the L1, and build a even larger, slower L2, and then we get the advantage that L2 is still faster than DRAM and we can prefetch into it.
This cache hierarchy tends to fit typical access patterns better as well - for many workloads most accesses will tend to be clumped together. For streaming workloads like video processing that won't fit in a L1 cache anyway, the algorithms are usually aware of row/column/striding impacts on cache utilization already.
There's probably more to consider, like SMP.
Now as to why cache sizes didn’t increase much once clock speeds stagnated and feature size continued to decline, I couldn’t say. But L3 caches didn’t used to exist, and L2 has gotten bigger.
Correct me if I'm wrong, but I don't think this is true. If you put instant memory a whole meter away it'll still only have a round trip of 6.6ns at the speed of light, which is approximately the latency of L2. Given how close L2 is, I don't think distance is a large factor of its latency.